Forward body biasing is a technique to increase performance of a Complementary Metal Oxide Semiconductor (CMOS) circuit, although power consumption may increase due to an increase in leakage current. During forward body biasing, the n-well of a pMOSFET (p-Metal-Oxide-Semiconductor Field Effect Transistor) is held at some voltage less than VCC, the supply rail voltage; and the p-substrate of an nMOSFET (which may be an isolated portion of a p-doped bulk substrate) is held at some voltage greater than VSS, the ground or substrate voltage.
Traditionally, the applied forward body bias is less in magnitude than a diode forward voltage drop, otherwise substrate diodes will become forward biased and the CMOS circuit may exhibit latchup, resulting in catastrophic behavior. However, with low voltage CMOS circuits in which the supply voltage is less than a diode forward voltage drop, for example about 0.5 V, it can be feasible to bias the n-wells and p-substrates at the supply rail and ground rail, respectively. This technique is often referred to as digital forward body biasing.